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256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O
256M (32Mx8bit) Hynix SDRAM Memory
Memory Cell Array
- Organized as 4banks of 8,388,608 x 8
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Aug. 2009 1
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Synchronous DRAM Memory 256Mbit H57V2582GTR-xxI Series
Document Title
256Mbit (32M x8) Synchronous DRAM
Revision History
Revision No. 0.1 1.0 History Preliminary Release Draft Date Jun. 2009 Aug. 2009 Remark
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DESCRIPTION
The Hynix H57V2582GTR Synchronous DRAM is 268,435,456bit CMOS Synchronous DRAM, ideally suited for the consumer memory applications which requires large memory density and high bandwidth. It is organized as 4banks of 8,388,608 x 8 I/O. Synchronous DRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Synchronous DRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x8 Input/ Output bus. All the commands are latched in synchronization with the rising edge of CLK. The Synchronous DRAM provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8 locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The Synchronous DRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compartible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, randon-access operation. Read and write accesses to the Hynix Synchronous DRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. All inputs are LVTTL compatible. Devices will have a VDD and VDDQ supply of 3.3V (nominal).
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256Mb Synchronous DRAM(32M x 8) FEATURES
Standard SDRAM Protocol Internal 4bank operation Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V All device pins are compatible with LVTTL interface Low Voltage interface to reduce I/O power 8,192 Refresh cycles / 64ms Programmable CAS latency of 2 or 3 Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst

-40oC ~ 85oC Operation Package Type : 54_Pin TSOPII This product is in compliance with the directive pertaining of RoHS.
ORDERING INFORMATION
Part Number H57V2582GTR-60I H57V2582GTR-75I H57V2582GTR-60J H57V2582GTR-75J Clock Frequency 166MHz 133MHz 166MHz 133MHz CAS Latency 3 3 3 3 Power Normal 3.3V Low Power 4Banks x 8Mbits x8 LVTTL Voltage Organization Interface
Note: 1. H57V2582GTR-XXI Series: Normal power & Commercial temp. 2. H57V2582GTR-XXJ Series: Low Power & Commercial temp.
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54 TSOP II Pin ASSIGNMENTS
VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45
VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
54 Pin TSOPII 400mil x 875mil 0.8mm pin pitch
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
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54_TSOPII Pin DESCRIPTIONS
SYMBOL CLK TYPE INPUT DESCRIPTION Clock : The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Clock Enable: Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Chip Select: Enables or disables all inputs except CLK, CKE and DQM Bank Address: Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address: RA0 ~ RA12, Column Address: CA0 ~ CA9 Auto-precharge flag: A10 Command Inputs: RAS, CAS and WE define the operation Refer function truth table for details Data Mask Data Input / Output: Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection : These pads should be left unconnected
CKE
INPUT
CS
INPUT
BA0, BA1
INPUT
A0 ~ A12
INPUT
RAS, CAS, WE DQM DQ0 ~ DQ7 VDD / VSS VDDQ / VSSQ NC
INPUT I/O I/O SUPPLY SUPPLY -
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FUNCTIONAL BLOCK DIAGRAM 8Mbit x 4banks x 8 I/O Synchronous DRAM
Self refresh logic & timer Internal Row Counter CLK CKE CS RAS CAS WE DQM State Machine Row Active Row Pre Decoder X Decorders 8M x8 Bank3 8M x8 Bank2 8M x8 Bank1 8M x8 Bank0 X Decorders DQ0 I/O Buffer & Logic Sense AMP & I/O Gate X Decorders
X Decoders
Refresh Column Active
Memory Cell Array
Column Pre Decoder Y decoerders
DQ7
Bank Select
Column Add Counter
A0 A1 Address Buffers
Address Register Burst Length
Burst Counter Pipe Line Control
A12 BA1 BA0
Mode Register
CAS Latency
Data Out Control
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ABSOLUTE MAXIMUM RATING
Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD supply relative to VSS Short Circuit Output Current Power Dissipation Symbol TA TSTG VIN, VOUT VDD, VDDQ IOS PD Rating -40 ~ 85 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 Unit
o o
C C
V V mA W
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VDD, VDDQ VIH VIL Min 3.0 2.0 -0.3 Max 3.6 VDDQ + 0.3 0.8 Unit V V V Note 1 1, 2 1, 3
Note: 1. All voltages are referenced to VSS = 0V. 2. VIH(Max) is acceptable VDDQ + 2V for a pulse width with <= 3ns of duration. 3. VIL(min) is acceptable -2.0V for a pulse width with <= 3ns of duration.
AC OPERATING TEST CONDITION (TA= -40 to 85oC, VDD=3.30.3V / VSS=0V)
Parameter AC Input High / Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement
Note: 1. See Next Page
Symbol VIH / VIL Vtrip tR / tF Voutref CL
Value 2.4 / 0.4 1.4 1 1.4 50
Unit V V ns V pF
Note
1
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VTT = 1.4V RT = 50 Ohom Output 50pF Output
Z0 = 50 Ohom
VTT = 1.4V RT = 50 Ohom
50pF
DC Output Load Circuit
AC Output Load Circuit
CAPACITANCE (f=1MHz)
Parameter CLK Input capacitance A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS, WE DQM Data input / output capacitance DQ0 ~ DQ7 Pin Symbol CI1 CI2 CI3 CI/O Min 2.0 2.0 2.0 3.5 Max 4.0 4.0 4.0 6.5 Unit pF pF pF pF
DC CHARACTERRISTICS I (TA= -40 to 85oC)
Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Symbol ILI ILO VOH VOL Min -1 -1 2.4 Max 1 1 0.4 Unit uA uA V V Note 1 2 IOH = -4mA IOL = +4mA
Note: 1. VIN = 0 to 3.6V, All other balls are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 3.6
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DC CHARACTERISTICS II (TA= -40 to 85oC)
Speed 166 90 2 2 133 70
Parameter Operating Current Precharge Standby Current in Power Down Mode Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode
Symbol IDD1 IDD2P IDD2PS
Test Condition Burst length=1, One bank active tRC tRC(min), IOL=0mA CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. tCK tCK(min), IOL=0mA All banks active tRC tRC(min), All banks active CKE 0.2V Normal Low Power
Unit mA mA mA
Note 1
IDD2N
15 mA 8 5 5 mA
IDD2NS IDD3P IDD3PS
Active Standby Current in Non Power Down Mode
IDD3N
28 mA 20 100 160 2 1 80 140 mA mA mA 1 2 3
IDD3NS Burst Mode Operating Current Auto Refresh Current Self Refresh Current IDD4 IDD5 IDD6
Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3. H57V2562GTR-XXI Series: Normal, H57V2562GTR-XXJ Series: Low Power
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AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter CL = 3 CL = 2 Symbol tCK3 tCK2 tCHW tCLW CL = 3 CL = 2 tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ CL = 3 CL = 2 tOHZ3 tOHZ2 166 Min 6.0 2.5 2.5 2.0 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.0 2.7 Max 1000 1000 5.4 5.4 Min 7.5 10 2.5 2.5 2.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.0 2.7 3 133 Max 1000 1000 5.4 6 5.4 6 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1 1 2 2 Note
System Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width Access Time From Clock Data-out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command Setup Time Command Hold Time CLK to Data Output in Low-Z Time CLK to Data Output in High-Z Time
Note:
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter.
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AC CHARACTERISTICS II
Parameter
(AC operating conditions unless otherwise noted)
Symbol Operation Auto Refresh tRC tRRC tRCD tRAS tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD CL = 3 CL = 2 tPROZ3 tPROZ2 tDPE tSRE tREF 2 0 2 3 1 1 166 Min 60 60 15 42 15 12 1 0 2 Max 100K 133 Min 63 63 15 42 15 15 1 0 2 Max 100K Unit ns ns ns ns ns ns CLK CLK CLK Note
RAS Cycle Time RAS to CAS Delay RAS Active Time RAS Precharge Time RAS to RAS Bank Active Delay CAS to CAS Delay Write Command to Data-In Delay Data-in to Precharge Command Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command Precharge to Data Output High-Z Power Down Exit Time Self Refresh Exit Time Refresh Time
tDPL + tRP 64 2 0 2 3 2 1 1 64 CLK CLK CLK CLK CLK CLK CLK ms 1
Note: 1. A new command can be given tRC after self refresh exit.
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BASIC FUNCTIONAL DESCRIPTION
Mode Register
BA1 0 BA0 0 A12 0 A11 0 A10 0 A9 OP Code A8 0 A7 0 A6 A5 A4 A3 BT A2 A1 A0
CAS Latency
Burst Length
OP Code
A9 0 1 Write Mode Burst Read and Burst Write Burst Read and Single Write
Burst Type
A3 0 1 Burst Type Sequential Interleave
CAS Latency
A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved
Burst Length
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Length A3 = 0 1 2 4 8 Reserved Reserved Reserved Full page A3=1 1 2 4 8 Reserved Reserved Reserved Reserved
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COMMAND TRUTH TABLE
Function Mode Register Set No Operation Device Deselect Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst stop DQM Auto Refresh Burst-Read Single-Write Self Refresh Entry Self Refresh Exit Precharge Power Down Entry Precharge Power Down Exit Clock Suspend Entry Clock Suspend Exit CKEn-1 H H H H H H H H H H H H H H H L H L H L CKEn X X X X X X X X X X X X H X L H L H L H L L L H L H L H L H L L L L X H X H X H X V X CS L L H L L L L L L L L RAS L H X L H H H H L L H X L L L X H X H X H X V H H H X H X H X H X V CAS L H X H L L L L H H H WE L H X H H H L L L L L X X X X X X V X X X X X X X X DQM X X X X Column Column Column Column X X ADDR A10 /AP X X Row Address L H L H H L X X X A9 Pin High (Other Pins OP code) X X X X X X 1 V V V V V X V BA Note
Op Code
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high.
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CURRENT STATE TRUTH TABLE (Sheet 1 of 4)
Current State Command CS RAS CAS WE L L L L idle L L L H L L L L Row Active L L L H L L L Read L L L L L L L L H H H X L L L L H H H X L L L L H H H L L H H L L H X L L H H L L H X L L H H L L H L H L H L H H X L H L H L H H X L H L H L H H X BA BA BA BA X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 Amax-A0 OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Action Set the Mode Register Start Auto or Self Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Start Write : optional AP(A10=H) Start Read : optional AP(A10=H) No Operation No Operation ILLEGAL ILLEGAL Termination Burst: Start the Precharge ILLEGAL Termination Burst: Start Write(optional AP) Termination Burst: Start Read(optional AP) Continue the Burst 4 8,9 8 13 13 4 4 3 3 13 13 7 4 6 6 5 Notes
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CURRENT STATE TRUTH TABLE
Current State Read CS RAS CAS WE H L L L L Write L L L H L L L Read with Auto Precharge L L L L H L L Write with Auto Precharge L L L L L H X L L L L H H H X L L L L H H H X L L L L H H H X X L L H H L L H X L L H H L L H X L L H H L L H X X L H L H L H H X L H L H L H H X L H L H L H H X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 X
(Sheet 2 of 4)
Command Amax-A0 X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X Description Device Deselect Mode Register Set Action Continue the Burst ILLEGAL 13 13 10 4 8 8,9 Notes
Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Termination Burst: Start the Precharge ILLEGAL Termination Burst: Start Write(optional AP) Termination Burst: Start Read(optional AP) Continue the Burst Continue the Burst ILLEGAL
13 13 4,12 4,12 12 12
Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL
13 13 4,12 4,12 12 12
Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst
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CURRENT STATE TRUTH TABLE
Current State CS RAS CAS WE L L L L Precharging L L L H L L L L Row Activating L L L H L L L L Write Recovering L L L L L L L H H H X L L L L H H H X L L L L H H H L L H H L L H X L L H H L L H X L L H H L L H L H L H L H H X L H L H L H H X L H L H L H H X BA BA BA BA X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1
(Sheet 3 of 4)
Command Amax-A0 OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X Description Mode Register Set ILLEGAL Action Notes 13 13
Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set No Operation: Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation: Bank(s) idle after tRP No Operation: Bank(s) idle after tRP ILLEGAL
4,12 4,12 4,12
13 13 4,12 4,11,1 2 4,12 4,12
Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: Row Active after tRCD No Operation: Row Active after tRCD ILLEGAL
13 13 4,13 4,12
Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation ILLEGAL ILLEGAL Start Write: Optional AP(A10=H) Start Read: Optional AP(A10=H) No Operation: Row Active after tDPL
9
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CURRENT STATE TRUTH TABLE
Current State Write Recovering CS RAS CAS WE H L L L Write Recovering with Auto Precharge L L L L H L L L L Refreshing L L L H L L L Mode Register Accessing L L L L H X L L L L H H H X L L L L H H H X L L L L H H H X X L L H H L L H X L L H H L L H X L L H H L L H X X L H L H L H H X L H L H L H H X L H L H L H H X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 X
(Sheet 4 of 4)
Command Amax-A0 X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X Description Device Deselect Mode Register Set Action No Operation: Row Active after tDPL ILLEGAL 13 13 4,13 4,12 4,12 4,9,12 Notes
Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: Precharge after tDPL No Operation: Precharge after tDPL ILLEGAL
13 13 13 13 13 13
Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: idle after tRC No Operation: idle after tRC ILLEGAL
13 13 13 13 13 13
Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: idle after 2 clock cycles No Operation: idle after 2 clock cycles
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Note : 1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge. 2. All entries assume that CKE was active during the preceding clock cycle. 3. If both banks are idle and CKE is inactive, then in power down cycle 4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address, depending on the state of that bank. 5. If both banks are idle and CKE is inactive, then Self Refresh mode. 6. Illegal if tRCD is not satisfied. 7. Illegal if tRAS is not satisfied. 8. Must satisfy burst interrupt condition. 9. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. Must mask preceding data which don't satisfy tDPL. 11. Illegal if tRRD is not satisfied 12. Illegal for single bank, but legal for other banks in multi-bank devices. 13. Illegal for all banks.
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CKE Enable(CKE) Truth TABLE
Current State CKE Previous Current Cycle Cycle H L L L L L L H L Power Down L H L X H H H H H L X H CS X H L L L L X X H L RAS X X H H H L X X X H L X X L H H H H All Banks Idle H H H H H H L L H H H H H L L L L L X X H L L L L H L L L L X X X H L L L X H L L L X
(Sheet 2 of 1)
Command CAS X X H H L X X X X H X L X X X X H L L X X H L L X WE X X H L X X X X X H X X L X X X X H L X X X H L X X X X X BA0, ADDR BA1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X Maintain Power Down Mode Refer to the idle State section of the Current State Truth Table Auto Refresh Mode Register Set Refer to the idle State section of the Current State Truth Table Entry Self Refresh Mode Register Set Power Down 4 4 3 3 3 4 3 3 3 ILLEGAL 2 INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down mode exit, all banks idle 1 2 Action Notes 1 2 2 2 2 2
Self Refresh
OP CODE
OP CODE X X
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CKE Enable(CKE) Truth TABLE
Current State CKE Previous Current Cycle Cycle H Any State other than listed above H CS RAS
(Sheet 2 of 2)
Command CAS WE BA0, ADDR BA1 X X Action Refer to operations of the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend Notes
X
X
X
X
H L L
L H L
X X X
X X X
X X X
X X X
X X X
X X X
Note : 1. For the given current state CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high. 3. The address inputs depend on the command that is issued. 4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state. 5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high and is maintained for a minimum 200usec.
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PACKAGE INFORMATION
e B
54
28
E1
E
27
1
DIE A2 D1 A1
millimeters Min 0.991 0.050 0.950 0.300 0.120 Typ 0.100 1.000 0.10 22.149 11.735 10.058 0.406 22.22 11.76 10.16 0.8 0.8 22.327 11.938 10.262 0.597 0.8720 0.4620 0.3950 0.0160 Max 1.194 0.150 1.050 0.400 0.210 Min 0.0390 0.0020 0.0374 0.012 0.0047 0.0039 0.0394 0.0039 0.8748 0.4630 0.4 0.0315 0.0315 0.8790 0.4700 0.4040 0.0235 -
C L1
CP
A
L
inches Typ Max 0.0470 0.0059 0.0413 0.016 0.0083
Symbol A A1 A2 B C CP D1 E E1 e L L1 alpha
0 / 5 (min / max)
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